1. Field of the Invention
This invention relates generally to a semiconductor memory devices, and particularly, to a fault-tolerant method and apparatus for multi-level semiconductor memory arrays.
2. Discussion of the Related Art
Large memory arrays suffer from the problem that some devices in the array will be bad, i.e., faulty. As a result, those devices which are bad cannot be correctly programmed. An ability to tolerate faults in a memory array, corresponding to a fault tolerance, would be desirable. A classical solution for providing fault tolerance to such memory arrays has been to add repair columns and/or rows to the array. In other words, redundant columns and/or rows are included in the memory array. A row (or column) containing a bad device can be disabled and a repair row (or column) can be activated to "fill in" for the disabled row (or column). A disadvantage of the use of such a repair row (or repair column) is that each bad device results in an entire row (or column) of devices being disabled. In the case of large memories with a large number rows (e.g. 256) and a large number of columns (e.g. 256), the latter solution of fault tolerance becomes inefficient and expensive.
A multi-level memory array is similar in structure to a typical memory array for non-volatile storage, however, the multi-level memory array is able to store a higher density of data. Storing higher density is achieved by storing between 2 and 8 bits of data for a single memory device of the memory array (i.e., 2-8 bits per single memory cell). For 2-bits of data, 2.sup.2 or 4 levels of charge can be stored per device. For 4-bits of data, 2.sup.4 or 16 levels of charge can be stored per device. Alternatively, for an n-bit storage cell, where n is an integer, 2.sup.n levels of charge can be stored per device.
With respect to multi-level and analog storage, the term multi-level storage refers to the storage, for example, of two bits (corresponding to four storage levels) per memory device in a memory array. Multi-level storage technology has been employed for both Flash-EEPROM, as well as DRAM. Multi-level storage for DRAM is discussed, for example, in the article entitled "A 4-Level Storage 4 Gb DRAM," Tatsunori Murotani et al., ISSCC97, paper TP 4.6, pages 74-75. Multi-level storage can reduce an effective cell size since it allows the storage of multiple voltage levels in a single memory cell functioning as a multi-bit memory. When four levels are stored in a single memory cell, the effective cell size is halved. With respect a multi-level storage DRAM, FIG. 1 illustrates the four-level storage concept (i.e., coding of a 2-bit memory and corresponding levels) in addition to conventional 2-level storage. With the four-level storage concept, a single memory cell stores four levels which corresponds to 2-bit data of "11", "10", "01", and "00". In conventional 2-level storage, the signal charge is one-half the maximum stored charge but in 4-level storage, the signal charge is one-sixth of the maximum stored charge.
Analog storage refers to the storage of more bits per device in a memory array, typically four to eight (4-8) bits (corresponding with 16-256 levels). Analog storage techniques have also been applied to both Flash-EEPROM, EEPROM, and specialized DRAM memories. With an analog flash memory, four to eight (4-8) bits of data can be stored on a single flash storage device, the storage device including, for example, a floating gate MOSFET. An example of a multi-level flash memory is described, for example, in the article "A Multilevel-Cell 32 Mb Flash Memory," M. Bauer et al., ISSCC95, paper TA 7.7, pages 132-133. A flash memory with multilevel cell significantly reduces the memory per-bit cost. For instance, a 32 Mb multilevel cell (MLC) Flash memory storing two bits of data per cell achieves 32 Mb memory storage capacity using 16M Flash memory cells. In MLC operation, the logical Flash memory cell achieves two bits per cell using four possible states, defined by four Flash cell threshold voltage ranges. The relationship between the threshold voltage ranges stored in the Flash memory cell and the corresponding logic levels is shown in FIG. 2. FIG. 2 illustrates a plot of four threshold voltage distributions (Vt), each with a separation range. The threshold voltages of read reference cells (R1, R2, and R3) are placed in the separation ranges between states. During read operations, read reference cells (not shown) are used in a binary search sensing scheme (BSSS). Threshold voltages of program verify reference cells (PV1, PV2, and PV3) are placed at the lower Vt edge of the various states. During program operations, the program verify cells are used to determine the lowest threshold voltage for states 2, 3 and 4. The maximum threshold voltage of state 0 (the erase state) is determined by the threshold voltage of an erase verify cell (EV) used during erase operations. Furthermore, programming of the memory cells to the various states is accomplished using an on-chip algorithm that applies a series of programming pulses to the Flash cell to adjust the threshold voltage by a predetermined amount. Typical threshold voltage distribution width for a state, shown in FIG. 2, is approximately 500 mV. After each program pulse, a program verify is performed by sensing the threshold voltage level of a cell using the BSSS with the program verify reference cells (PV1, PV2, and PV3) replacing the read reference cells (R1, R2, and R3).
In the article "A 3.3V 128 Mb Multi-Level NAND Flash Memory for Mass Storage Applications," Tae-Sung Jung et al., ISSCC96, Paper TP 2.1, pages 32-33, a 128 Mb multi-level NAND flash memory stores two bits per cell by tight programmed cell threshold voltage (Vth) control. Program states have 0.4V Vth distribution and a 0.8V separation gap. Incremental-step pulse programming (ISPP) gives narrower Vth distribution with a smaller stepping voltage. In addition, in the article "A 98 mm.sup.2 3.3V 64 Mb Flash Memory with FN-NOR Type 4-level Cell," Masayoshi Ohkawa et al., ISSCC96, paper TP2.3, pages 36-37, a 64 Mb flash memory with a multi-level cell and 64-memory-cell parallel programming is described. Drain-voltage controlled multilevel programming (DCMP) is used for simultaneous multi-level programming in the flash memory chip. To implement the DCMP, a parallel multi-level verify (PMV) circuit and the compact multi-level sense amplifier (CMS), which enable a 64-memory-cells parallel programming operation (program/program verify), are used. Additional discussion and details may be found in the cited articles, and thus not further discussed herein.
As discussed above, a prescribed number of levels, corresponding to bits of data, can be stored using a single flash storage device of an analog flash memory. Analog flash memory thus allows a significantly denser memory structure than that possible using conventional digital or multi-level memory techniques.
FIG. 3 illustrates a floating gate MOSFET device 10 having a source 12 and drain 14 region formed in a bulk silicon substrate 16. A channel region 18 extends between the source and drain regions. The floating gate MOSFET device 10 further includes a floating gate 20 and a control gate 22 positioned over the channel 18, separated from one another and the bulk silicon via an insulative layer (not shown). An electrical schematic of the floating gate MOSFET device is illustrated in FIG. 4. In addition, an exemplary electrical circuit 30 for use in reading a stored value from the floating gate MOSFET device using conductance is shown in FIG. 4. In the circuit 30 of FIG. 5, an analog-to-digital converter 32 converts an analog value into an appropriate digital value corresponding to the value stored in the floating gate device 34. Circuit 30 further includes an op-amp 36 and a current source 38. Floating gate MOSFET storage devices are known in the art and thus only briefly discussed herein.
Still further, the use of floating gate technology for long-term analog storage is known in the art, for example, as discussed in "Flash-Based Programmable Nonlinear Capacitor for Switched-Capacitor Implementations of Neural Networks," A. Kramer et al., IEDM 94-449, pages 449-452. In addition, an example of an electrically erasable non-volatile memory cell (FLASH EEPROM) designed for use in analog computing devices in the charge domain is disclosed in U.S. Pat. No. 5,592,418, assigned to the assignee of the present invention, incorporated herein by reference.
In view of prior methods as discussed above for providing fault tolerance to memory arrays, it would thus be desirable to provide an improved method and apparatus for handling defective devices of a memory array, especially with respect to a sequential access array.